1) Field of the Invention
The invention relates to methods and resulting electrically programmable read-only memories (EPROM) and electrically erasable programmable read only-memories EEPROM) device structures.
2) Description of the Prior Art
The mechanism of hot electron emission into gate oxide and gate had been identified by A. Phillips et al. in the 1975 IEDM Technical Digest, p. 39. Since then, the phenomena was intensively investigated by T. Ning et al. in J. Applied Physics. 1977, Vol. 48. p. 286, and by many other scientists. Until identification of hot electron emission, electrical programmable memories (EPROM) utilized memory structures very similar to those of Channel Hot Electron EPROM's, but which employed the avalanche breakdown mechanism to program the memory cell by Frohman-Bentchkowsky: p-channel in 1971 ISSCC, p. 80, "A Fully decoded 2048 bit Electrically-Programmable MOS-ROM", and n-channel in an article entitled "FAMOS--A New Semiconductor Charge Storage Device", Solid State Electronics, 1974, Vol. 17, p. 517. Immediately after discovery of the hot electron emission mechanism into a silicon gate, this injection mechanism was applied for programming of n-MOSFET EPROM cells by J. Barnes et al. in 1976 IEDM, p. 177, "Operation and Characterization of N-channel EPROM cell" and P. Salsbury in 1977 ISSCC, p. 186, "High Performance MOS EPROM using a stack gate cell", J. Barnes showed two basic types of the double polysilicon CHE EPROM transistors in FIG. 1A stack gate transistor 100a and FIG. 1B split gate transistor 100b. Both transistors have N+ source junction 104, N+ drain junction 106, p-substrate 101, channel gate oxide 120, floating gate 140, poly oxide 130, and control gate 145. Transistor 100b has a split channel consisting of a section 110 whose conductivity is controlled by floating gate 140 and control gate 145, in series with a section 118, whose conductivity is controlled by control gate 145. Passivation layer 900 is shown in FIG. 1B. In both type transistors 100a and 100b, programming takes place by injection of hot electron near the silicon surface and near the drain junction.
A numerical model correctly predicting hot electron emission into floating gate was established by Cheming Hu in IEDM 1970, p. 223, `Lucky-Electron Model of Channel Hot Electron Emission`. FIG. 2 presents the cross sectional view of a typical double polysilicon stack gate EPROM transistor 200, which was used to explain his lucky model. The transistor is an NMOS transistor with source 204, drain 206. substrate 201, floating gate 240 and control gate 245. When a voltage Vcg is applied to control gate 245, over the floating gate 240 but insulated by dielectric layer 230, capacitive coupling causes the voltage of the floating gate to increase proportionally to the capacitance ratio (=coupling ratio) of Ccg-fg/(Ccg-fg+Cfg-si), where Ccg-fg is the control gate-floating gate capacitance and Cfg-si is the floating gate-channel and source/drain capacitance. Once the floating gate voltage exceeds the threshold voltage, electrons begin to flow from source to drain. The horizontal electric field due to the drain-source potential difference accelerates horizontal movement of electrons in the channel which is near to the silicon surface, typically within a 10 nm depth. The electrons gain energy and momentum from the horizontal field reaching maximum energy near the drain edge 206. A small portion of electrons obtain higher energy than the tunnel oxide (220) barrier height. When electron energy exceeds the insulator barrier height, it becomes possible that electrons may be emitted into the insulator 220 and reach the floating gate polysilicon 240 if the momentum (motion) of electrons is redirected upward to the floating gate by acoustic phonon scattering without suffering energy loss. It was observed that the probability of injection from the channel into the polysilicon is less than the orders of IE-6 to IE-9. Also the model suggested that channel hot electron emission into a floating gate would be negligible if Vd-Vs is less than 2.5V. no matter how small the channel length or junction depth.
That the probability of channel electron onto the floating gate is so small is disadvantageous in many ways. The disadvantages in the prior art channel hot electron injection for EPROM and EEPROM memory operation are:
a) The drain voltage has to be raised much higher (for example 5V or higher) than theoretical requirement of 2.5.about.3V since the probability that electrons are redirected upward by acoustic scattering is so small that many hot electrons have to be generated by increased drain voltage. PA1 b) The control gate voltage must be high (9.about.10V for a coupling ratio of 0.6.about.0.5), because the injected electrons require an assisting electric field to reach the floating gate polysilicon (the floating gate voltage needs to exceed the drain voltage). When the floating gate voltage is lower than the drain voltage, electrons that were injected into the oxide get repelled back to the drain. PA1 c) The program time to store electrons onto the floating gate is long, typically on the order of micro-seconds compared to the read access time on the ten nano-second order, since the injection efficiency of electrons is less than 1E-6, PA1 d) Since the injection current is so small and the injection current depends on both the drain voltage and the control gate voltage, it is difficult to control the level of retained electrons each time in the program cycle. PA1 e) High voltage devices to decode the control gate are required in the memory array. The higher the control gate voltage is, the longer the channel length must be with thicker gate oxide. This induces a density penalty and becomes a major obstacle in the scaled technology. PA1 f) Extra hot electrons due to the higher drain voltage lead to quick oxide wear out and less endurance, since the higher energy electrons damage more oxide crystal lattice and creates traps. PA1 g) Power consumption and the drain current are high due to low injection efficiency, and the high voltage requirement for the drain and control gate. PA1 a) Extra process steps to build a triple polysilicon structure involve extra depositions of polysilicon for erase, and a dielectric layer for tunnel erase. Extra complicated structures and masking steps are also involved to selectively remove electrons from the floating gate to erase polysilicon. not to tunnel from the erase gate to control gate polysilicon. This penalizes not only an increase in process complexity, but also the memory cell density. PA1 b) Extra circuitry to generate the erase voltage is required. In order to minimize the impact of extra circuitry on density, the block size of erase must be relatively large. Large block size of erase reduces the overall lifetime of the memory array, since the large block size increases unnecessary program and erase cycles.
In electrically erasable and programmable read-only memories (EEPROM), electrons stored on the floating gate are removed electrically by applying the appropriate voltages to the transistor terminals. There are two erase approaches to removing electrons from the floating gate in EEPROM. One approach is with the double polysilicon EEPROM cell, which removes electrons from the floating gate to downward silicon (i.e., either source, drain diffusions or substrate). Another approach is with the triple polysilicon EEPROM cell which removes electrons from the floating gate to a separate third gate.
The double polysilicon cell approach for EEPROM is described by G. Samachusa et al., in 1987 IEEE Journal of Solid Sate Circuits, Vol. SC-22, No. 5, p. 676, "128K Flash EEPROM using double polysilicon technology". Variations of this double polysilicon cell are described by H. Kume et al. in an article titled. "Flash-Erase EEPROM cell with an Asymmetric Source and Drain Structure", Technical Digest of the IEEE International Electron Device Meeting, December 1987, p. 560, and by V. N. Kynett et al. in an article titled, "An In-system Reprogrammable 256k CMOS Flash Memory", Digest of Technical papers, IEEE International Solid-State Circuits Conference, February 1988, p. 132.
A typical double polysilicon stack gate EEPROM cell by H. Kume, which removeselectrons from floating gate to downward silicon, is shown in FIG. 3A. Erase in double polysilicon EEPROM transistor 300a is achieved through tunnel oxide 320, between floating gate 340 and source diffusion junction 304 when the electric field across the tunnel oxide exceeds the critical electric field for F-N tunneling of .about.10 MV/cm. In typical voltage applications for erase, the tunnel oxide is 10 nm, the diffusion junction is 12V, the control gate is 0V and the drain voltage is floating. Since this approach requires high voltage on the source junction, the junction is susceptible to avalanche breakdown. In order to protect against breakdown, the source junction is made deeper than drain junction (the drain junction must kept shallow to create a high electric field at drain junction edge for Hot Channel Electron). This stack gate cell is a variation of EPROM cell 100a in FIG. 1A, but with an asymmetrical deep source junction. It is noted that the double poly split gate transistor 100b offers a junction on only one side and so cannot be used for EE applications requiring asymmetric diffusions.
The triple polysilicon transistor overcomes this is claimed to solve the density disadvantages associated with a deep junction for scaled-down memory technologies. A triple polysilicon device is described by J. Kupec et al., in 1980 IEDM Technical Digest, p. 602, in an article entitled, "Triple Level Polysilicon EEPROM with Single Transistor per Bit". An improvement to the Kupec device was proposed by F. Masuoka and H. Iizuka in U.S. Pat. No. 4,531,203 issued Jul. 23, 1985. Variations on the same cell are described by C. K. Kuo and S. C. Tsaur in U.S. Pat. No. 4,561,004 issued Dec. 24, 1985 by A. T. Wu et al., in the 1986 SEDPM Technical Digest, p. 584 in an article entitled, "A Novel High-speed, 5-V Programming EPROM structure with source-side injection", and by E. Harari in U.S. Pat. No. 5,198,380 issued Mar. 30, 1993.
All of these various triple polysilicon memory cells utilize one of the polysilicon levels as an erase gate. An erase gate passes through each memory cell transistor closely adjacent to the surface of the floating gate, but insulated therefrom by a thin tunnel dielectric. Charge is then removed from the floating gate to the erase gate, when appropriate voltages are applied to all of the transistor elements. Among various triple polysilicon EEPROM cells, the EEPROM transistor 300b with the third polysilicon for erase by Kupec is shown in FIG. 3B. In transistor 300b, electrons stored on the floating gate 340 are removed from the side wall of the floating gate to the third polysilicon 350. Typical voltages applied to each node during erase are the following: 12-15V on the triple erase polysilicon for 20 nm ONO 325, and 0V for the second polysilicon of control gate 345 and the diffusion junctions of 304 and 306. The highest junction voltage is about 5V on the drain, during program, Thus junction avalanche breakdown and junction leakage problems do not exist in the triple polysilicon EEPROM transistor. The solution of a triple polysilicon transistor has its own cost however. The disadvantages: